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Atmega 128 Highlights

  • 3 different programming spaces – program, data, and eeprom

  • In system programmable 128 k is organized as 64k * 16 words. These are addressed by the 16 bit program counter.

  • In the Atmega 128 mode, there is (256 special bytes + 4096) of data memory which is also used as Register and IO space.   The first 32 locations addre ss the Register file, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 4096 locations address the internal data SRAM.

  • The first 64 bytes of SRAM can be addressed by IN, OUT instructions.   The remaining SRAM databytes can be addressed only ST, STS, STD and LD, LDS, LDD instructions.   The I/O memory space contains 64 addresses which can be accessed directly, or as the Data Space locations following those of the Register file, $20 - $5F.

  • The interrupt vectors have priority in accordance with their interrupt vector position. The lower the interrupt vector address the higher the priority.

  • The status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

  • The general purpose registers are not physically implemented in SRAM. They can howerver be addressed as the first 32 bytes of SRAM.   This memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file.

  • All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.

  • When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts.All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

  • There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

  • When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

  • The Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

  • When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.

  • lo8 and hi8 give low and high 8 bits of a 16 bit pointer in gcc

  • In gcc there is a difference between SIGNAL and INTERRUPT, the first instruction in the SIGNAL routine is 'cli' thus disabling all interrupts while executing the ISR. INTERRUPT's first instruction is 'sei' allowing further interrupt processing

  • When using VMLAB remember to shift the data segments. You can use the __auto.mak of the WinAVR Demo supplied with VMLAB as an example.

  • With VMLAB you can add differnet NRZ data patterns for different keys by using the “+” option. See VMLAB help for example.

  • Adding 2 separate patterns for the same pin seems to mess VMLAB up.

  • When picking preamble bytes for serial communication pick those that when shifted cannot become another preamble byte.

  • Use PORT for output and PIN for input.

  • Using avarice with avr-insight

  • C:\projects\scd\raytheon\dev\singleDirBuild>avarice -j /dev/com1 --file aspss.elf -P atmega128 -d localhost:1212

  • avr-insight
    Goto target and set target as gdb-tcp, localhost 1212
    Connect to target from run menu
    load main
    set breakpoint
    can set other breakpoints in source

  • To use avarice to connect to target without downloading omit the –file option. You will have to specify source in avr-insight or gdb though.

  • Fuses 0xFF, 0x1CE4 for JTAG, OCD, SPIEN enabled, not 103 compatibility mode, brown out 2.7 V, 1024 Boot flash section, BOOTRST 0 bootrst enabled

  • For Atmega 128 MOSI is mapped to PDI and MISO to PDO. Do not wire the ISP connector to pins designated MOSI and MISO.
    White -2
    Green -3

    Blue – SCK 11

  • Yello-w RST

  • Make sure the STK 500 board volatage is set to 3 V before using it to program a 3 V part and no power is supplied to the board being programmed.

  • Register is a reserved word in C

  • You have to write 1 to TXC bit to clear the TXC flag !!!!